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ESD Sensitivity of electronic devices

As the human body was originally the most common and damaging source of electrostatic discharge, the most common measurement of ESD sensitivity is by Human Body Model (HBM) electrostatic discharge. In this test a charged 100pF capacitor is discharged into the device via a 1500W resistor. The 100pF capacitor simulates charged stored on the average human body, and the resistor simulates the resistance of the human body and skin. 61340-5-1, if fully implemented, aims to protect devices down to 100V HBM sensitivity. 

The ESD sensitivity of devices is given as an "ESD withstand voltage", which is the maximum test voltage at which the device did not suffer damage. Typical HBM withstand voltages of various device technologies are given in the following table. 

Device type

ESD withstand voltage sensitivity (V) HBM

MR heads, RF FETs

10 - 100

PIN diodes, laser diodes

100 - 300V

Pre - 1990 VLSI

400 - 1000V

Modern VSLI

1000 - 3000V


1500 - 3000V

CMOS B Series

2000 - 5000 V

Linear MOS

800 - 4000 V

Small geometry older bipolar

600 - 6000 V

Small geometry modern bipolar

2000 - 8000 V

Power bipolar

7000 - 25000 V

Film resistor

1000 - 5000 V

Unfortunately many semiconductor device suppliers do not publish the ESD withstand date of their products on their datasheets and it can be very difficult to find this information for particular devices. The table above can only be considered a rough guide.

As component technology progresses, internal device sizes reduce and become more ESD sensitive. Many modern components are protected by on-chip protection circuits, without which they would be extremely sensitive. Untile recently in most cases the design goal has been to increase the device ESD withstand voltage to 2 kV HBM, 200V MM and 500V CDM. In some cases these goals cannot be met for various reasons - there is often a tradeoff between ESD protection and device performance.

More recently various organisations have questioned the need for such robust on-chip ESD protection networks when a normal ESD Program protects devices down to 100V HBM. On-chip protection carries a cost of substantial chip area needed fro the protection networks, especially for high pin count devices. There can also be a penalty of added design and development time needed to achieve the required protection performane. More recently it has become difficult to achieve this ESD protection performance with some technologies. The Industry Council on ESD Target Levels is an independent organisation of ESD experts including device manufacturers, equipment manufacturers, CEMs, consultants and others with a mission to review the requirements for modern device ESD robustness for handling in an ESD Protected Area. Since 2007 they have published White Papers giving a case for lowering device HBM and MM protection requirements to 1kV HBM and 30V MM, and CDM protection requirements to 250V. They have also published a White Paper on misconceptions regarding system level ESD susceptibility.


Terms and conditons

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Where you can get the 61340-5-1 and other standards.